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APPLICATION NOTE
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XCR3128: 128 Macrocell CPLD
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Product Specification
Introduction
* * * Industry's first TotalCMOSTM PLD - both CMOS design and process technologies Fast Zero Power (FZPTM) design technique provides ultra-low power and very high speed IEEE 1149.1-compliant, JTAG Testing Capability - Four pin JTAG interface (TCK, TMS, TDI, TDO) - IEEE 1149.1 TAP Controller - JTAG commands include: Bypass, Sample/Preload, Extest, Usercode, Idcode, HighZ 3.3V, In-System Programmable (ISP) using the JTAG interface - On-chip supervoltage generation - ISP commands include: Enable, Erase, Program, Verify - Supported by multiple ISP programming platforms High speed pin-to-pin delays of 10 ns Ultra-low static power of less than 100 A 100% routable with 100% utilization while all pins and all macrocells are fixed Deterministic timing model that is extremely simple to use Four clocks available Programmable clock polarity at every macrocell Support for asynchronous clocking Innovative XPLATM architecture combines high-speed with extreme flexibility 1000 erase/program cycles guaranteed 20 years data retention guaranteed Logic expandable to 37 product terms PCI compliant Advanced 0.5 E2CMOS process Security bit prevents unauthorized access Design entry and verification using industry standard and Xilinx CAE tools Reprogrammable using industry standard device programmers Innovative control term structure provides either sum terms or product terms in each logic block for: - Programmable 3-state buffer - Asynchronous macrocell register preset/reset - Programmable global 3-state pin facilitates "bed of nails" testing without using logic resources - Available in PLCC, VQFP, and PQFP packages - Available in both commercial and industrial grades
Description
The XCR3128 CPLD (Complex Programmable Logic Device) is the third in a family of CoolRunner(R) CPLDs from Xilinx. These devices combine high speed and zero power in a 128 macrocell CPLD. With the FZP design technique, the XCR3128 offers true pin-to-pin speeds of 10 ns, while simultaneously delivering power that is less than 100 A at standby without the need for ` turbo-bits' or other power-down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD. These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. For 5V applications, Xilinx also offers the high speed XCR5128 CPLD that offers these features in a full 5V implementation. The Xilinx FZP CPLDs utilize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 10 ns PAL path with five dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2.5 ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 12.5 ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density. The XCR3128 CPLDs are supported by industry standard CAE tools (CadencE/OrCAD, Exemplar Logic, Mentor, Synopsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses a Xilinx developed tool, XPLA Professional (available on the Xilinx web site). 1
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XCR3128: 128 Macrocell CPLD
The XCR3128 CPLD is electrically reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others. The XCR3128 also includes an industry-standard, IEEE 1149.1, JTAG interface through which in-system programming (ISP) and reprogramming of the device is supported. by a Zero-power Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each logic block is essentially a 36V16 device with 36 inputs from the ZIA and 16 macrocells. Each logic block also provides 32 ZIA feedback paths from the macrocells and I/O pins. From this point of view, this architecture looks like many other CPLD architectures. What makes the CoolRunner family unique is what is inside each logic block and the design technique used to implement these logic blocks. The contents of the logic block will be described next.
XPLA Architecture
Figure 1 shows a high level block diagram of a 128 macrocell device implementing the XPLA architecture. The XPLA architecture consists of logic blocks that are interconnected
MC0 MC1 I/O MC15 16 16 16 16 LOGIC BLOCK 36 36 LOGIC BLOCK
MC0 MC1 I/O MC15
MC0 MC1 I/O MC15 16 16 ZIA LOGIC BLOCK 36 36 LOGIC BLOCK 16 16 LOGIC BLOCK 36 36 LOGIC BLOCK
MC0 MC1 I/O MC15
MC0 MC1 I/O MC15 16 16
MC0 MC1 I/O MC15 16 16
MC0 MC1 I/O MC15 16 16 16 16 LOGIC BLOCK 36 36 LOGIC BLOCK
MC0 MC1 I/O MC15
SP00464
Figure 1: Xilinx XPLA Architecture
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XCR3128: 128 Macrocell CPLD Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic block contains control terms, a PAL array, a PLA array, and 16 macrocells. the six control terms can individually be configured as either SUM or PRODUCT terms, and are used to control the preset/reset and output enables of the 16 macrocells' flip-flops. The PAL array consists of a programmable AND array with a fixed OR array, while the PLA array consists of a programmable AND array with a programmable OR array. The PAL array provides a high speed path through the array, while the PLA array provides increased product term density. Each macrocell has five dedicated product terms from the PAL array. The pin-to-pin tPD of the XCR3128 device through the PAL array is 10 ns. If a macrocell needs more than five product terms, it simply gets the additional product terms from the PLA array. The PLA array consists of 32 product terms, which are available for use by all 16 macrocells. The additional propagation delay incurred by a macrocell using one or all 32 PLA product terms is just 2.5 ns. So the total pin-to-pin tPD for the XCR3128 using six to 37 product terms is 12.5 ns (10 ns for the PAL + 2.5 ns for the PLA).
36 ZIA INPUTS
CONTROL 5
6
PAL ARRAY
PLA ARRAY
(32) SP00435A
Figure 2: Xilinx XPLA Logic Block Architecture
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TO 16 MACROCELLS
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XCR3128: 128 Macrocell CPLD Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in the CoolRunner family. The macrocell consists of a flip-flop that can be configured as either a D- or T-type. A D-type flip-flop is generally more useful for implementing state machines and data buffering. A T-type flip-flop is generally more useful in implementing counters. All CoolRunner family members provide both synchronous and asynchronous clocking and provide the ability to clock off either the falling or rising edges of these clocks. These devices are designed such that the skew between the rising and falling edges of a clock are minimized for clocking integrity. There are four clocks available on the XCR3128 device. Clock 0 (CLK0) is designated as the "synchronous" clock and must be driven by an external source. Clock 1 (CLK1), Clock 2 (CLK2), and Clock 3 (CLK3) can either be used as a synchronous clock (driven by an external source) or as an asynchronous clock (driven by a macrocell equation). The timing for asynchronous clocks is different in that the tCO time is extended by the amount of time that it takes for the signal to propagate through the array and reach the clock network, and the tSU time is reduced. Two of the control terms (CT0 and CT1) are used to control the Preset/Reset of the macrocell's flip-flop. The Preset/Reset feature for each macrocell can also be disabled. Note that the Power-on Reset leaves all macrocells in the "zero" state when power is properly applied. The other four control terms (CT2-CT5) can be used to control the Output Enable of the macrocell's output buffers. The reason there are as many control terms dedicated for the Output Enable of the macrocell is to insure that all CoolRunner devices are PCI compliant. The macrocell's output buffers can also be always enabled or disabled. All CoolRunner devices also provide a Global 3-state (GTS) pin, which, when enabled and pulled Low, will 3-state all the outputs of the device. This pin is provided to support "In-circuit Testing" or "Bed-of-nails" testing. There are two feedback paths to the ZIA: one from the macrocell, and one from the I/O pin. The ZIA feedback path before the output buffer is the macrocell feedback path, while the ZIA feedback path after the output buffer is the I/O pin ZIA path. When the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented in the macrocell. When the I/O pin is used as an input, the output buffer will be 3-stated and the input signal will be fed into the ZIA via the I/O feedback path, and the logic implemented in the buried macrocell can be fed back to the ZIA via the macrocell feedback path. It should be noted that unused inputs or I/Os should be properly terminated (see the section on "Terminations" on page 9 in this data sheet and the application note Terminating Unused I/O Pins in Xilinx XPLA1 and XPLA2 CoolRunnerTM CPLDs).
TO ZIA
PAL LA D/T INIT (P or R) CLK0 CLK0 CLK1 CLK1 CLK2 CLK2 CLK3 CLK3 CT0 CT1 GND CT2 CT3 CT4 CT5 VCC GND SP00457 Q
GTS GND
Figure 3: XCR3128 Macrocell Architecture
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XCR3128: 128 Macrocell CPLD Simple Timing Model
Figure 4 shows the CoolRunner Timing Model. The CoolRunner timing model looks very much like a 22V10 timing model in that there are three main timing parameters, including tPD, tSU, and t CO. In other competing architectures, the user may be able to fit the design into the CPLD, but is not sure whether system timing requirements can be met until after the design has been fit into the device. This is because the timing models of competing architectures are very complex and include such things as timing dependencies on the number of parallel expanders borrowed, sharable expanders, varying number of X and Y routing channels used, etc. In the XPLA architecture, the user knows up front whether the design will meet system timing requirements. This is due to the simplicity of the timing model.
TotalCMOS Design Technique for Fast Zero Power
Xilinx is the first to offer a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its Sum of Products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs which are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 5 and Table 1 showing the ICC vs. Frequency of our XCR3128 TotalCMOS CPLD (data taken w/eight up/down, loadable 16 bit counters at 3.3V, 25C).
INPUT PIN
tPD_PAL = COMBINATORIAL PAL ONLY tPD_PLA = COMBINATORIAL PAL + PLA
OUTPUT PIN
INPUT PIN
REGISTERED tSU_PAL = PAL ONLY tSU_PLA = PAL + PLA
D
Q
REGISTERED tCO
OUTPUT PIN
GLOBAL CLOCK PIN
SP00441
Figure 4: CoolRunner Timing Model
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140
120
100
ICC (mA)
80
60
40
20
0 0 20 40 FREQUENCY (MHz) SP00471 60 80 100
Figure 5: ICC vs. Frequency @ VCC = 3.3V, 25C
Table 1: ICC vs. Frequency (VCC = 3.3V, 25C) Frequency (MHz) Typical ICC (mA) 0 .03 1 .06 20 12 40 24 60 35 80 46 100 63
JTAG Testing Capability
JTAG is the commonly-used acronym for the Boundary Scan Test (BST) feature defined for integrated circuits by IEEE Standard 1149.1. This standard defines input/output pins, logic control functions, and commands which facilitate both board and device level testing without the use of specialized test equipment. BST provides the ability to test the external connections of a device, test the internal logic of the device, and capture data from the device during normal operation. BST provides a number of benefits in each of the following areas: * Testability - Allows testing of an unlimited number of interconnects on the printed circuit board - Testability is designed in at the component level - Enables desired signal levels to be set at specific pins (Preload) *
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Data from pin or core logic signals can be examined during normal operation Reliability - Eliminates physical contacts common to existing test fixtures (e.g., "bed-of-nails") - Degradation of test equipment is no longer a concern - Facilitates the handling of smaller, surface-mount components - Allows for testing when components exist on both sides of the printed circuit board Cost - Reduces/eliminates the need for expensive test equipment - Reduces test preparation time - Reduces spare board inventories
The Xilinx XCR3128's JTAG interface includes a TAP Port and a TAP Controller, both of which are defined by the IEEE 1149.1 JTAG Specification. As implemented in the Xilinx 6
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XCR3128: 128 Macrocell CPLD
XCR3128, the TAP Port includes four of the five pins (refer to Table 2) described in the JTAG specification: TCK, TMS, TDI, and TDO. The fifth signal defined by the JTAG specification is TRST* (Test Reset). TRST* is considered an optional signal, since it is not actually required to perform BST or ISP. The Xilinx XCR3128 saves an I/O pin for general purpose use by not implementing the optional TRST* signal in the JTAG interface. Instead, the Xilinx XCR3128 supports the test reset functionality through the use of its power up reset circuit, which is included in all Xilinx CPLDs. The pins associated with the power up reset circuit should connect to an external pull-up resistor to keep the JTAG signals from floating when they are not being used. In the Xilinx XCR3128, the four mandatory JTAG pins each require a unique, dedicated pin on the device. However, if JTAG and ISP are not desired in the end-application, these pins may instead be used as additional general I/O pins. The decision as to whether these pins are used for JTAG/ISP or as general I/O is made when the JEDEC file is generated. If the use of JTAG/ISP is selected, the dedicated pins are not available for general purpose use. However, unlike competing CPLD's, the Xilinx XCR3128 does allow the macrocell logic associated with these dedicated pins to be used as buried logic even when JTAG/ISP is selected. Table 3 defines the dedicated pins used by the four mandatory JTAG signals for each of the XCR3128 package types. The JTAG specifications defines two sets of commands to support boundary-scan testing: high-level commands and low-level commands. High-level commands are executed via board test software on an a user test station such as automated test equipment, a PC, or an engineering workstation (EWS). Each high-level command comprises a sequence of low level commands. These low-level commands are executed within the component under test, and therefore must be implemented as part of the TAP Controller design. The set of low-level boundary-scan commands implemented in the Xilinx XCR3128 is defined in Table 4. By supporting this set of low-level commands, the XCR3128 allows execution of all high-level boundary-scan commands.
Table 2: JTAG Pin Description PIN TCK NAME Test Clock Output DESCRIPTION Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins, respectively. TCK is also used to clock the TAP Controller state machine. Serial input pin selects the JTAG instruction mode. TMS should be driven high during user mode operation. Serial input pin for instructions and test data. Data is shifted in on the rising edge of TCK. Serial output pin for instructions and test data. Data is shifted out on the falling edge of TCK. The signal is tri-stated if data is not being shifted out of the device.
TMS TDI TDO
Test Mode Select Test Data Input Test Data Output
Table 3: XCR3128 JTAG Pinout by Package Type Device XCR3128 84-pin PLCC 100-pin PQFP 100-pin VQFP 128-pin TQFP 160-pin PQFP (Pin Number / Macrocell #) TMS TDI 23 / 48 (C15) 14 / 32 (B15) 17 / 48 (C15) 6 / 32 (B15) 15 / 48 (C15) 4 / 32 (B15) 21 / 48 (C15) 8 / 32 (B15) 22 / 48 (C15) 9 / 32 (B15)
TCK 62 / 96 (F15) 64 / 96 (F15) 62 / 96 (F15) 82 / 96 (F15) 99 / 96 (F15)
TDO 71 / 112 (G15) 75 / 112 (G15) 73 / 112 (G15) 95 / 112 (G15) 112/ 112 (G15)
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Table 4: XCR3128 Low-Level JTAG Boundary-Scan Commands Instruction (Instruction Code) Register Used Sample/Preload (0010) Boundary-Scan Register Extest (0000) Boundary-Scan Register Bypass (1111) Bypass Register Idcode (0001) Boundary-Scan Register Description The mandatory SAMPLE/PRELOAD instruction allows a snapshot of the normal operation of the component to be taken and examined. It also allows data values to be loaded onto the latched parallel outputs of the Boundary-Scan Shift-Register prior to selection of the other boundary-scan test instructions. The mandatory EXTEST instruction allows testing of off-chip circuitry and board level interconnections. Data would typically be loaded onto the latched parallel outputs of Boundary-Scan Shift-Register using the Sample/Preload instruction prior to selection of the EXTEST instruction. Places the 1 bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through the selected device to adjacent devices during normal device operation. The Bypass instruction can be entered by holding TDI at a constant high value and completing an Instruction-Scan cycle. Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. The IDCODE instruction permits blind interrogation of the components assembled onto a printed circuit board. Thus, in circumstances where the component population may vary, it is possible to determine what components exist in a product. The HIGHZ instruction places the component in a state in which all of its system logic outputs are placed in an inactive drive state (e.g., high impedance). In this state, an in-circuit test system may drive signals onto the connections normally driven by a component output without incurring the risk of damage to the component. The HighZ instruction also forces the Bypass Register between TDI and TDO. * Field Support - Easy remote upgrades and repair - Support for field configuration, re-configuration, and customization
HighZ (0101) Bypass Register
3.3V In-System Programming (ISP)
ISP is the ability to reconfigure the logic and functionality of a device, printed circuit board, or complete electronic system before, during, and after its manufacture and shipment to the end customer. ISP provides substantial benefits in each of the following areas: * Design - Faster time-to-market - Debug partitioning and simplified prototyping - Printed circuit board reconfiguration during debug - Better device and board level testing Manufacturing - Multi-Functional hardware - Reconfigurability for test - Eliminates handling of "fine lead-pitch" components for programming - Reduced Inventory and manufacturing costs - Improved quality and reliability
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The Xilinx XCR3128 allows for 3.3V, in-system programming/reprogramming of its EEPROM cells via its JTAG interface. An on-chip charge pump eliminates the need for externally-provided supervoltages, so that the XCR3128 may be easily programmed on the circuit board using only the 3.3-volt supply required by the device for normal operation. A set of low-level ISP basic commands implemented in the XCR3128 enable this feature. The ISP commands implemented in the Xilinx XCR3128 are specified in Table 5 Please note that an ENABLE command must precede all ISP commands unless an ENABLE command has already been given for a preceding ISP command and the device has not gone through a Test-Logic/Rest TAP Controller State. See also Table 5 Programming Specifications.
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Table 5: Programming Specifications Symbol DC Parameters VCC supply program/verify VCCP ICCP ICC limit program/verify VIH Input voltage (High) VIL Input voltage (Low) VSOL Output voltage (Low) VSOH Output voltage (High) TDO_IOL Output current (Low) TDO_IOH Output current (High) AC Parameters fMAX CLK maximum frequency PWE Pulse width erase PWP Pulse width program PWV Pulse width verify INIT Initialization time TMS_SU TMS setup time before TCK = TDI_SU TDI setup time before TCK = TMS_H TMS hold time after TCK = TDI_H TDI hold time after TCK = TDO_CO TDO valid after TCK Parameter Min. 3.0 2.0 0.8 0.5 2.4 8 -8 10 100 10 10 100 10 10 25 25 40 Max. 3.6 200 Unit V mA V V V V mA mA MHz ms ms s s ns ns ns ns ns
Terminations
The CoolRunner XCR3128 CPLDs are TotalCMOS devices. As with other CMOS devices, it is important to consider how to properly terminate unused inputs and I/O pins when fabricating a PC board. Allowing unused inputs and I/O pins to float can cause the voltage to be in the linear region of the CMOS input structures, which can increase the power consumption of the device. The XCR3128 CPLDs have programmable on-chip pull-down resistors on each I/O pin. These pull-downs are automatically activated by the fitter software for all unused I/O pins. Note that an I/O macrocell used as buried logic that does not have the I/O pin used for input is considered to be unused, and the pull-down resistors will be turned on. We recommend that any unused I/O pins on the XCR3128 device be left unconnected. There are no on-chip pull-down structures associated with the dedicated input pins. Xilinx recommends that any unused dedicated inputs be terminated with external 10k pull-up resistors. These pins can be directly connected to VCC or GND, but using the external pull-up resistors maintains maximum design flexibility should one of the unused dedicated inputs be needed due to future design changes. When using the JTAG/ISP functions, it is also recommended that 10k pull-up resistors be used on each of the pins associated with the four mandatory JTAG signals. Let-
ting these signals float can cause the voltage on TMS to come close to ground, which could cause the device to enter JTAG/ISP mode at unspecified times. See the application notes JTAG and ISP Overview for Xilinx XPLA1 and XPLA2 CPLDs and Terminating Unused I/O Pins in Xilinx XPLA1 and XPLA2 CoolRunner CPLDs for more information.
JTAG and ISP Interfacing
A number of industry-established methods exist for JTAG/ISP interfacing with CPLD's and other integrated circuits. The Xilinx XCR3128 supports the following methods: * * * * * * PC parallel port Workstation or PC serial port Embedded processor Automated test equipment Third party programmers High-End JTAG and ISP tools
A Boundary-Scan Description Language (BSDL) description of the XCR3128 is also available from Xilinx for use in test program development. For more details on JTAG and ISP for the XCR3128, refer to the related application note: JTAG and ISP Overview for Xilinx XPLA1 and XPLA2 CPLDs.
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Absolute Maximum Ratings1
Symbol VCC VI VOUT IIN IOUT TJ Tstr
Notes: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. 2. The chip supply voltage must rise monotonically.
Parameter Supply voltage2 Input voltage Output voltage Input current Output current Maximum junction temperature Storage temperature
Min. -0.5 -1.2 -0.5 -30 -100 -40 -65
Max. 7.0 VCC + 0.5 VCC + 0.5 30 100 150 150
Unit V V V mA mA C C
Operating Range
Product Grade Commercial Industrial Temperature 0 to +70C -40 to +85C Voltage 3.3V 10% 3.3V 10%
DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0C TAMB +70C; 3.0V VCC 3.6V Symbol VIL VIH VI VOL VOH II IOZ ICCQ1 ICCD1, 2 IOS CIN CCLK CI/O
Notes: 1. See Table 1 on page 6 for typical values. 2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing. 3. Typical values, not tested.
Parameter Input voltage low Input voltage high Input clamp voltage Output voltage low Output voltage high Input leakage current 3-stated output leakage current Standby current Dynamic current Short circuit output current3 Input pin capacitance3 Clock input capacitance3 I/O pin capacitance3
Test Conditions VCC = 3.0V VCC = 3.6V VCC = 3.0V, IIN = -18 mA VCC = 3.0V, IOL = 8 mA VCC = 3.0V, IOH = -8 mA VIN = 0 to VCC VIN = 0 to VCC V CC = 3.6V, TAMB = 0C VCC = 3.6V, TAMB = 0C at 1 MHz VCC = 3.6V, TAMB = 0C at 50 MHz One pin at a time for no longer than 1 second T AMB = 25C, f = 1 MHz T AMB = 25C, f = 1MHz T AMB = 25C, f = 1MHz
Min. 2.0
Max. 0.8 -1.2 0.5
2.4 -10 -10
-50
10 10 60 2 50 -100 8 12 10
Unit V V V V V A A A mA mA mA pF pF pF
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AC Electrical Characteristics1 For Commercial Grade Devices
Commercial: 0C TAMB +70C; 3.0V VCC 3.6V Symbol tPD_PAL tPD_PLA tCO tSU_PAL tSU_PLA tH tCH tCL tR tF fMAX1 fMAX2 fMAX3 tBUF tPDF_PAL tPDF_PLA tCF tINIT tER tEA tRP tRR
Notes: 1. Specifications measured with one output switching. See Figure 6 and Table 6 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output CL = 5 pF.
Parameter Propagation delay time, input (or feedback node) to output through PAL Propagation delay time, input (or feedback node) to output through PAL + PLA Clock to out (global synchronous clock from pin) Setup time (from input or feedback node) through PAL Setup time (from input or feedback node) through PAL + PLA Hold time Clock High time Clock Low time Input Rise time Input Fall time Maximum FF toggle rate 2 1/(tCH + tCL) Maximum internal frequency 2 1/(tSUPAL + t CF) Maximum external frequency 2 1/(tSUPAL + t CO) Output buffer delay time Input (or feedback node) to internal feedback node delay time through PAL Input (or feedback node) to internal feedback node delay time through PAL+PLA Clock to internal feedback node delay time Delay from valid VDD to valid reset Input to output disable 3 Input to output valid Input to register preset Input to register reset
10 Min. 2 3 2 6 8.5 Max. 10 12.5 7 Min. 2 3 2 7 9.5
12 Max. 12 14.5 8 Min. 2 3 2 8 10.5
15 Max. 15 17.5 9
Unit ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns s ns ns ns ns
0 3 3 20 20 167 87 77 2 3 1.5 0.5 11 5.5 50 12.5 12.5 14 14 125 74 66 2 3 4 4
0 4 4 20 20 125 65 59 1.5 10.5 13 6.5 50 14 14 16 16 2 3
0
20 20
1.5 13.5 16 7.5 50 17 17 19 19
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DC Electrical Characteristics For Industrial Grade Devices
Industrial: -40C TAMB +85C; 3.0V VCC 3.6V Symbol VIL VIH VI VOL VOH II IOZ ICCQ1 ICCD1, 2 IOS CIN CCLK CI/O
Notes: 1. See Table 1 on page 6 for typical values. 2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs DISabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing. 3. Typical values, not tested.
Parameter Input voltage Low Input voltage High Input clamp voltage Output voltage Low Output voltage High Input leakage current 3-stated output leakage current Standby current Dynamic current Short circuit output current3 Input pin capacitance3 Clock input capacitance3 I/O pin capacitance3
Test Conditions VCC = 3.0V VCC = 3.6V VCC = 3.0V, IIN = -18 mA VCC = 3.0V, IOL = 8 mA VCC = 3.0V, IOH = -8 mA VIN = 0 to VCC VIN = 0 to VCC V CC = 3.6V, TAMB = -40C VCC = 3.6V, TAMB = -40C at 1 MHz VCC = 3.6V, TAMB = -40C at 50 MHz One pin at a time for no longer than 1 second T AMB = 25C, f = 1 MHz T AMB = 25C, f = 1MHz T AMB = 25C, f = 1MHz
Min. 2.0
Max. 0.8 -1.2 0.5
2.4 -10 -10
-50
10 10 75 2 50 -130 8 12 10
Unit V V V V V A A A mA mA mA pF pF pF
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AC Electrical Characteristics1 For Industrial Grade Devices
Industrial: -40C TAMB +85C; 3.0V VCC 3.6V Symbol tPD_PAL tPD_PLA tCO tSU_PAL tSU_PLA tH tCH tCL tR tF fMAX1 fMAX2 fMAX3 tBUF tPDF_PAL tPDF_PLA tCF tINIT tER tEA tRP tRR
Notes: 1. Specifications measured with one output switching. See Figure 6 and Table 8 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output CL = 5 pF.
Min. Propagation delay time, input (or feedback node) to output through PAL 2 Propagation delay time, input (or feedback node) to output through 3 PAL + PLA Clock to out (global synchronous clock from pin) 2 Setup time (from input or feedback node) through PAL 7 Setup time (from input or feedback node) through PAL + PLA 9.5 Hold time Clock High time 3 Clock Low time 3 Input Rise time Input Fall time Maximum FF toggle rate2 1/(tCH + tCL) 167 2 Maximum internal frequency 1/(t SUPAL + tCF) 77 Maximum external frequency2 1/(t SUPAL + tCO) 69 Output buffer delay time Input (or feedback node) to internal feedback node delay time through 2 PAL Input (or feedback node) to internal feedback node delay time through 3 PAL+PLA Clock to internal feedback node delay time Delay from valid VCC to valid reset Input to output disable 3 Input to output valid Input to register preset Input to register reset
Parameter
12 Max. 12 14.5 7.5 Min. 2 3 2 8 10.5 4 4 20 20 125 65 59 1.5 10.5 13 6 50 13 13 15 15 2 3
15 Max. 15 17.5 9
Unit ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns s ns ns ns ns
0
0
20 20
1.5 13.5 16 7.5 50 15.5 15.5 17 17
13
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DS034 (v1.2) August 10, 2000
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XCR3128: 128 Macrocell CPLD
Switching Characteristics
The test load circuit and load values for the AC Electrical Characteristics are illustrated below.
VCC
S1
COMPONENT R1 R2
R1
VALUES 390 390 35 pF
C1
VIN VOUT
MEASUREMENT
R2 C1
S1 Open Closed Closed
S2 Closed Closed Closed
tPZH tPZL tP
S2
Note: For tPHZ and tPLZ C = 5 pF, and 3-state levels are measured 0.5V from steady-state active level.
SP00477
VDD = 3.3V, 25C 9.1
+3.0V 90%
8.7
10% 0V tR 1.5ns tF 1.5ns
tPD_PAL (ns) 8.3
SP00368 MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
7.9
Input Pulses
Figure 7: Voltage Waveform
7.5 1 2 4 8 12 16 NUMBER OF OUTPUTS SWITCHING SP00466A
Table 6: tPD_PAL vs. Number of Outputs Switching (VCC = 3.3 V, T = 25C) Number Of Outputs Typical (ns) 1 7.9 2 8 4 8.1 8 8.3 12 8.4 16 8.6
Figure 6: tPD_PAL vs. Output Switching
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XCR3128: 128 Macrocell CPLD
Pin Function And Layout
XCR3128: 100-pin and 160-pin PQFP Pin Function Table
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Function PQFP 100-pin
I/O-A5 I/O-A4 I/O-A2 I/O-A0 VCC I/O-B15 (TDI) I/O-B13 I/O-B12 I/O-B10 I/O-B8 I/O-B7 I/O-B5 GND I/O-B4 I/O-B2 I/O-B0 I/O-C15 (TMS) I/O-C13 I/O-C12 VCC I/O-C10 I/O-C8 I/O-C7 I/O-C5 I/O-C4 I/O-C2 I/O-C0 GND I/O-D15 I/O-D13 I/O-D12 I/O-D10 I/O-D8 I/O-D7 I/O-D5 VCC I/O-D4 I/O-D2 I/O-D0/CK2 GND
160-pin
NC NC NC NC NC NC NC VCC I/O-B15 (TDI) I/O-B13 I/O-B12 I/O-B11 I/O-B10 I/O-B8 I/O-B7 I/O-B5 GND I/O-B4 I/O-B3 I/O-B2 I/O-B0 I/O-C15 (TMS) I/O-C13 I/O-C12 I/O-C11 VCC I/O-C10 I/O-C8 I/O-C7 I/O-C5 I/O-C4 I/O-C3 I/O-C2 NC NC NC NC NC NC NC
Pin #
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Function PQFP 100-pin
VCC I/O-E0/CLK1 I/O-E2 I/O-E4 GND I/O-E5 I/O-E7 I/O-E8 I/O-E10 I/O-E12 I/O-E13 I/O-E15 VCC I/O-F0 I/O-F2 I/O-F4 I/O-F5 I/O-F7 I/O-F8 I/O-F10 GND I/O-F12 I/O-F13 I/O-F15 (TCK) I/O-G0 I/O-G2 I/O-G4 VCC I/O-G5 I/O-G7 I/O-G8 I/O-G10 I/O-G12 I/O-G13 I/O-G15 (TDO) GND I/O-H0 I/O-H2 I/O-H4 I/O-H5
160-pin
I/O-C0 GND I/O-D15 NC NC NC NC I/O-D13 I/O-D12 I/O-D11 I/O-D10 I/O-D8 I/O-D7 I/O-D5 VCC I/O-D4 I/O-D3 I/O-D2 I/0-D0/CLK2 GND VCC I/0-E0/CLK1 I/O-E2 I/O-E3 I/O-E4 GND I/0-E5 I/0-E7 I/0-E8 I/0-E10 I/O-E11 I/0-E12 I/0-E13 NC NC NC NC I/O-E15 VCC I/O-F0
Pin #
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Function PQFP 100-pin
I/O-H7 I/O-H8 I/O-H10 VCC I/O-H12 I/O-H13 I/O-H15 GND IN0/CK0 IN2/gtsn IN1 IN3 VCC I/O-A15/CK3 I/O-A13 I/O-A12 GND I/O-A10 I/O-A8 I/O-A7 -
160-pin
NC NC NC NC NC NC NC I/O-F2 I/O-F3 I/O-F4 I/O-F5 I/O-F7 I/O-F8 I/O-F10 GND I/O-F11 I/O-F12 I/O-F13 I/O-F15 (TCK) I/O-G0 I/O-G2 I/O-G3 I/O-G4 VCC I/O-G5 I/O-G7 I/O-G8 I/O-G10 I/O-G11 I/O-G12 I/O-G13 I/O-G15 (TDO) GND NC NC NC NC NC NC NC
Pin #
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
Function PQFP 100-pin
-
160-pin
I/O-H0 I/O-H2 I/O-H3 NC NC NC NC I/O-H4 I/O-H5 I/O-H7 I/O-H8 I/O-H10 VCC I/O-H11 I/O-H12 I/O-H13 I/O-H15 GND IN0/CK0 IN2/gtsn IN1 IN3 VCC I/O-A0/CK3 I/O-A13 I/O-A12 I/O-A11 GND I/O-A10 I/O-A8 I/O-A7 I/O-A5 I/O-A4 NC NC NC NC I/O-A3 I/O-A2 I/O-A0
15
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XCR3128: 128 Macrocell CPLD XCR3128: 84-pin PLCC, 100-Pin VQFP, and 128-pin TQFP Pin Function Table
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Function PLCC
IN1 IN3 VCC I/O-A15/ CLK3 I/O-A13 I/O-A12 GND I/O-A10 I/O-A7 I/O-A5 I/O-A4 I/O-A2 VCC I/O-B15 (TDI) I/O-B12 I/O-B10 I/O-B8 I/O-B7 GND I/O-B4 I/O-B2 I/O-B0 I/O-C15 (TMS) I/O-C13 I/O-C12 VCC I/O-C10 I/O-C7 I/O-C5 I/O-C4 I/O-C2 GND
VQFP
I/O-A2 I/O-A0 VCC I/O-B15 (TDI) I/O-B13 I/O-B12 I/O-B10 I/O-B8 I/O-B7 I/O-B5 GND I/O-B4 I/O-B2 I/O-B0 I/O-C15 (TMS) I/O-C13 I/O-C12 VCC I/O-C10 I/O-C8 I/O-C7 I/O-C5 I/O-C4 I/O-C2 I/O-C0 GND I/O-D15 I/O-D13 I/O-D12 I/O-D10 I/O-D8 I/O-D7
TQFP
I/O-A3 I/O-A2 I/O-A0 NC NC NC VCC I/O-B15 (TDI) I/O-B13 I/O-B12 I/O-B11 I/O-B10 I/O-B8 I/O-B7 I/O-B5 GND I/O-B4 I/O-B3 I/O-B2 I/O-B0 I/O-C15 (TMS) I/O-C13 I/O-C12 I/O-C11 VCC I/O-C10 I/O-C8 I/O-C7 I/O-C5 I/O-C4 I/O-C3 I/O-C2
Pin #
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Function PLCC
I/O-D15 I/O-D12 I/O-D10 I/O-D8 I/O-D7 VCC I/O-D4 I/O-D2 I/O-D0/C LK2 GND VCC I/O-E0/C LK1 I/O-E2 I/O-E4 GND I/O-E7 I/O-E8 I/O-E10 I/O-E12 I/O-E15 VCC I/O-F2 I/O-F4 I/O-F5 I/O-F7 I/O-F10 GND I/O-F12 I/O-F13 I/O-F15 (TCK) I/O-G0 I/O-G2
VQFP
I/O-D5 VCC I/O-D4 I/O-D2 I/O-D0/ CLK2 GND VCC I/O-E0/ CLK1 I/O-E2 I/O-E4 GND I/O-E5 I/O-E7 I/O-E8 I/O-E10 I/O-E12 I/O-E13 I/O-E15 VCC I/O-F0 I/O-F2 I/O-F4 I/O-F5 I/O-F7 I/O-F8 I/O-F10 GND I/O-F12 I/O-F13 I/O-F15 (TCK) I/O-G0 I/O-G2
TQFP
NC NC NC I/O-C0 GND I/O-D15 I/O-D13 I/O-D12 I/O-D11 I/O-D10 I/O-D8 I/O-D7 I/O-D5 VCC I/O-D4 I/O-D3 I/O-D2 I/O-D0/C LK2 GND VCC I/O-E0/ CLK1 I/O-E2 I/O-E3 I/O-E4 GND I/O-E5 I/O-E7 I/O-E8 I/O-E10 I/O-E11 I/O-E12 I/O-E13
Pin #
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
Function PLCC
I/O-G4 VCC I/O-G7 I/O-G8 I/O-G10 I/O-G12 I/O-G15 (TDO) GND I/O-H2 I/O-H4 I/O-H5 I/O-H7 I/O-H10 VCC I/O-H12 I/O-H13 I/O-H15 GND IN0/ CLK0 IN2/gtsn -
VQFP
I/O-G4 VCC I/O-G5 I/O-G7 I/O-G8 I/O-G10 I/O-G12 I/O-G13 I/O-G15 (TDO) GND I/O-H0 I/O-H2 I/O-H4 I/O-H5 I/O-H7 I/O-H8 I/O-H10 VCC I/O-H12 I/O-H13 I/O-H15 GND IN0/CLK0 IN2/gtsn IN1 IN3 VCC
TQFP
I/O-E15 VCC I/O-F0 NC NC NC I/O-F2 I/O-F3 I/O-F4 I/O-F5 I/O-F7 I/O-F8 I/O-F10 GND I/O-F11 I/O-F12 I/O-F13 I/O-F15 (TCK) I/O-G0 I/O-G2 I/O-G3 I/O-G4 VCC I/O-G5 I/O-G7 I/O-G8 I/O-G10
Pin #
97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
Function PLCC
-
VQFP
I/O-A8 I/O-A7 I/O-A5 I/O-A4 -
TQFP
NC NC NC I/O-H0 I/O-H2 I/O-H3 I/O-H4 I/O-H5 I/O-H7 I/O-H8 I/O-H10 VCC I/O-H11 I/O-H12 I/O-H13 I/O-H15 GND IN0/CLK0 IN2/gtsn IN1 IN3 VCC I/O-A15/ CLK3 I/O-A13 I/O-A12 I/O-A11 GND I/O-A10 I/O-A8 I/O-A7 I/O-A5 I/O-A4
I/O-A15/C I/O-G11 LK3 I/O-A13 I/O-A12 GND I/O-A10 I/O-G12 I/O-G13 I/O-G15 (TDO) GND
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XCR3128: 128 Macrocell CPLD 84-pin PLCC
11 1 75 1
128-pin TQFP
128 103
12
74
102
PLCC
TQFP LQFP
32
54 38 33 53 SP00467A 39 64 SP00469B 65
100-pin PQFP 160-pin PQFP
100 81 160 1
PQFP QFP
121
80 1 120
PQFP 30 51
40
81
31
50
41 SP00468A
80
SP00470B
100-pin VQFP
100 76
1
75
VQFP TQFP
25
51
26
50 SP00485A
17
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DS034 (v1.2) August 10, 2000
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XCR3128: 128 Macrocell CPLD
Ordering Information
Example: XCR3128 -10 PC 84 C
Device Type Speed Options Temperature Range Number of Pins Package Type
Speed Options -15: 15 ns pin-to-pin delay -12: 12 ns pin-to-pin delay -10: 10 ns pin-to-pin delay
Temperature Range C = Commercial, TA = 0C to +70C I = Industrial, TA = -40C to +85C Packaging Options PC84: 84-pin PLCC PQ100: 100-pin PQFP VQ100: 100-pin VQFP TQ128: 128-pin TQFP PQ160: 160-pin PQFP
Component Availability
Pins Type Code XCR3128 84 Plastic PLCC PC84 C, I C, I C 100 Plastic PQFP PQ100 C, I C, I C Plastic VQFP VQ100 C, I C, I C 128 Plastic TQFP TQ128 C, I C, I C 160 Plastic PQFP PQ160 C, I C, I C
-15 -12 -10
Revision Table
Date 8/4/99 2/10/00 8/10/00 Version # 1.0 1.1 1.2 Revision Initial Xilinx release Converted to Xilinx format and updated. Updated pinout tables.
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